The present disclosure relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present disclosure relates to a method of shallow trench isolation (STI) formation using amorphous carbon.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
A variety of different isolation techniques can be employed to provide electrical isolation between devices fabricated on the same piece of silicon. One isolation technique is local oxidation of silicon (LOCOS). LOCOS is often employed to electrically insulate or isolate various portions or structures of the semiconductor device from other portions of the device. Another isolation technique for isolating devices of the same type is shallow trench isolation (STI).
In general, conventional STI formation uses a thick layer of nitride as a hard mask. The nitride thickness depends on the lithography printing capability, normally at the range of 1400-1800 Angstroms (xc3x85). This nitride layer or hard mask is patterned and the substrate beneath it is etched to form trenches in accordance with the pattern. After the trenches are formed, they are filled with an insulative material such as silicon dioxide (SiO2).
The nitride provides a chemical-mechanical polish (CMP) stop layer for subsequent etching steps and can serve as an anti-reflective coating (ARC). The trench filled material (e.g., silicon dioxide) is removed after trench oxide gap fill. A chemical mechanical polish (CMP) selective to silicon dioxide with the nitride layer as an etch stop is conventionally used to remove the trench fill material. Nitride can be detected in the polishing of a tetraethyl orthosilicate (TEOS) using the hardness characteristic of nitride. An over-polish can be utilized into the nitride, assuming a known polish rate. After the trench filled material is removed, the nitride layer is removed according to a CMP process selective to nitride silicon.
After the nitride layer is removed, an uneven formation or relatively large step may be created on the top surface of the substrate. The large step is due to the height of the oxide gap fill in the trench which generally has the same height as the original nitride layer. Disadvantageously, residual material or xe2x80x9cpoly stringerxe2x80x9d from subsequent deposition, masking, and photolithographic steps can form along the large step. Failure to remove this material can lead to unwanted electrical shorting paths between adjacent lines.
Unfortunately, over-polish of nitride suffers from lack of a well-defined end-point signal. It is likely then that the over-polish can leave too much nitride or, alternatively, polish too far and damage the active region in the substrate. If too much nitride is left, there is a large active-field step between the nitride-covered active and the STI. Such a large active-field step can result in poor patterning at step edges and on the field. It is difficult to know when the over-polish has gone too far because the hardness of the nitride is relatively similar to silicon.
Such challenges are not limited to STI formation, but can also apply to the formation processes of gate trenches, conductive line trenches or any of a variety of integrated circuit features.
Thus, there is a need to provide a more defined end-point signal for accurate polishing in integrated circuit fabrication. Further, there is a need to use amorphous carbon as a sacrificial polish stop layer in STI formation for improved chemical mechanical polish (CMP) controllability. Even further, there is a need to improve the active-field step in a CMP.
An exemplary embodiment relates to a method of shallow trench isolation (STI) formation using amorphous carbon as a sacrificial polish stop layer. The method can include polishing a silicon dioxide layer located above a wafer, polishing portions of the silicon dioxide layer located in a field area and portions of an amorphous carbon layer located in an active area. Portions of the amorphous carbon layer are polished down to a hard polish stop layer. The method can also include ashing away residual amorphous carbon from the amorphous carbon layer.
Another exemplary embodiment relates to a method of feature formation using amorphous carbon as a sacrificial layer to form a defined end point and improved field step. The method can include polishing portions of an amorphous carbon layer located in active regions and polishing portions of an oxide layer located in field regions. Portions of the amorphous carbon layer are polished down to a stop layer located below the amorphous carbon layer and the oxide layer is polished down to approximately the same cross-sectional level as the stop layer. The method can also include ashing away any remaining portions of the amorphous carbon layer.
Another exemplary embodiment relates to a method of more accurately polishing layers during formation of an integrated circuit feature in a trench. The method can include forming a trench in a trench region, providing an amorphous carbon layer above a polish stop layer in a region proximate the trench region, depositing a material above the amorphous carbon layer and in the trench, polishing the material and the amorphous carbon layer down to a horizontal cross-section defined by the polish stop layer, and ashing away any remaining amorphous carbon from the polished amorphous carbon layer.